| 摘要 |
A system and method perform a two-pass fault simulation on an original design representation including a software-modeled design element and a hardware-modeled design element. Logic simulation generates input stimulus for a port on the boundary of the software-modeled design element and the hardware-modeled design element, where such ports are output ports of the software-modeled design element and input ports of the hardware-modeled design element. The input stimulus is merged with test patterns for the original design representation. A modified design representation is generated by replacing the software-modeled design element with a nonfunctional block. Most or all possible faults in the hardware-modeled design representation are seeded. The modified design representation is fault simulated in a first pass using the merged input stimulus and test patterns. Any unseeded faults from the first pass and other possible faults in the software-modeled design representation are then seeded and the original design representation is fault simulated in a second pass. The fault coverage results of the two passes are aggregated to generate an overall fault coverage for the original design representation.
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