| 摘要 |
A structure (300) for determining an amount of line edge roughness (LER) on a patterned feature (310) includes a plurality of source regions (304) and drain regions (306) formed in a semiconductor substrate (303), with each of the source and drain regions (304, 306) having a channel (320) therebetween. The source regions (304) are electrically isolated from each other and the drain regions (306) are electrically isolated from each other, respectively. The patterned feature of interest (310) is formed over a gate oxide, extends over the channels (320) in a direction which is transverse to the source regions (304) and the drain regions (306), and forms a common gate (310) for a plurality of transistors (302a-302n) formed with the plurality of source regions (304) and drain regions (306). The plurality of transistors (302a-302n) are activated to conduct current therethrough by placing a predetermined voltage on the common gate (310) and the currents of the plurality of transistors (302a-302n) are used to determine the line edge roughness (LER) of the patterned feature 310.
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