发明名称 |
Semiconductor memory device |
摘要 |
A semiconductor memory device includes a plurality of memory banks each including a plurality of memory cells, one of which is selectable in accordance with an address signal; a memory bit line for receiving a read voltage from the selected memory cell; a reference cell for outputting a reference voltage; a reference bit line for receiving the reference voltage; a comparison and amplification device for amplifying a difference between a voltage from the memory bit line and a voltage from the reference bit line; and a load capacitance adjusting device for providing a third load capacitance to the reference bit line so that a first load capacitance between the selected memory cell and the comparison and amplification device is substantially equal to a second load capacitance between the reference cell and the comparison and amplification device.
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申请公布号 |
US6370060(B2) |
申请公布日期 |
2002.04.09 |
申请号 |
US20010836949 |
申请日期 |
2001.04.17 |
申请人 |
SHARP KABUSHIKI KAISHA |
发明人 |
TAKATA MASAHIRO;TAKATA HIDEKAZU |
分类号 |
G11C17/18;G11C7/14;G11C16/06;G11C16/28;(IPC1-7):G11C16/06 |
主分类号 |
G11C17/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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