发明名称 |
Delta sigma D/A converter |
摘要 |
The problem of the present invention is, in a plural-number order delta sigma D/A converter, not to cause click noise upon performing mute operation at no-signal input idling and hence to eliminate the necessity of a circuit for removing this.In order to perform sequence operation for rendering zero an output signal by lowering the order of a loop filter in order when stopping the operation of a plural-number order delta sigma D/A converter, 1st-order differentiators corresponding to each order and switch means for rendering inputs to these 1st-order differentiators zero are provided in the loop filter.
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申请公布号 |
US6369731(B1) |
申请公布日期 |
2002.04.09 |
申请号 |
US20000724170 |
申请日期 |
2000.11.28 |
申请人 |
NIPPON PRECISION CIRCUITS INC. |
发明人 |
TAKEDA MINORU;HANADA YOSHIHIRO;TOYAMA AKIRA |
分类号 |
H03M1/08;H03M3/02;H03M7/00;(IPC1-7):H03M1/66;H03M3/00 |
主分类号 |
H03M1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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