发明名称 |
Parity determining apparatus and method |
摘要 |
A parity determining circuit is used to determine the parity of a binary word. The binary word is represented by a sequence of optical bit slots. Each bit slot defines a respective one of two complementary logical states. The circuit includes: an input pulse stream generator that generates copies of the binary word; a combining device that receives two binary words, offsets one word with respect to the other, and then combines them to form a combination word; and a circuit that applies a copy of the original binary word together with the combination word to the combining device a number of times in succession. This results in a combination word that has a number of bits in the same logical state and that indicates the parity of the binary word.
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申请公布号 |
US6369921(B1) |
申请公布日期 |
2002.04.09 |
申请号 |
US20000623320 |
申请日期 |
2000.08.31 |
申请人 |
BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY |
发明人 |
BLOW KEITH JAMES;POUSTIE ALISTAIR JAMES;MANNING ROBERT JOHN |
分类号 |
G02F3/00;H03M13/11;H04L1/00;H04L1/20;(IPC1-7):G06E1/04;H04B10/08 |
主分类号 |
G02F3/00 |
代理机构 |
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代理人 |
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主权项 |
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