发明名称 Method and apparatus for performing N bit by 2*N-1 bit signed multiplications
摘要 A method and apparatus for performing N bit by 2*N (or 2*N-1) bit signed multiplication using two N bit multiply instructions. According to one aspect of the invention, a method for performing signed multiplication of A times B (where B has N bits and A has N*2 bits) is described. In this method, Ahigh and Alow respectively represent the most and least significant halves of A. According to this method, Alow is logically shifted right by one bit to generate Alow>>1. Then, Alow>>1 is multiplied by B using signed multiplication to generate a first partial result. In addition, a second partial result is generated by performing signed multiplication of Ahigh times B. One or both of the first and second partial results is shifted to align the first and second partial results for addition, and then the addition is performed to generate a final result representing A multiplied by B.
申请公布号 US6370559(B1) 申请公布日期 2002.04.09
申请号 US19990354004 申请日期 1999.07.13
申请人 INTEL CORPORTION 发明人 HOFFMAN NATHANIEL
分类号 G06F7/52;G06F9/30;G06F9/302;(IPC1-7):G06F7/52 主分类号 G06F7/52
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