| 摘要 |
An apparatus is configured to monitor the source and target clocks (e.g., receive and transmit clocks, respectively, each from different clock domains) to determine if the respective frequencies of the clocks lead to more data being received by a buffer used to communicate between the two devices than is transmitted from that buffer. Upon detecting such a situation, a staging buffer is used to pre-read entries from the buffer and transfer these entries to the output of the buffer. Effectively, the transmit data pipeline may be dynamically extended by a stage comprising the staging buffer. The staging buffer continues to be used until a synchronization event occurs. A synchronization event allows for the transmit logic to "catch up" by, e.g., processing two items of information from the buffer concurrently.
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