发明名称 Degenerate network for PLD and plane
摘要 A programmable logic device comprising one or more first stages and one or more second stages. The one or more first stages may comprise one or more gates of a first type each having a first number of inputs. The one or more second stages may comprise one or more gates of a second type each having a second number of inputs, wherein said first and second stages are interlaced.
申请公布号 US6369609(B1) 申请公布日期 2002.04.09
申请号 US20000567455 申请日期 2000.05.08
申请人 CYPRESS SEMICONDUCTOR CORP. 发明人 IGHANI RAMIN;NAYAK ANUP
分类号 H03K19/173;(IPC1-7):H03K19/173;H03K19/177 主分类号 H03K19/173
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