METHOD FOR FORMING MULTI-LAYER PATTERN OF HIGH INTEGRATED SEMICONDUCTOR DEVICE

摘要

PURPOSE: A method for forming a multi-layer pattern of a high integrated semiconductor device is provided to simplify a fabricating process by minimizing an anti-reflective layer process. CONSTITUTION: A transistor(120) is formed on a semiconductor substrate(100). The first interlayer dielectric(140) is formed on the semiconductor substrate(100) including the transistor(120). A bit line contact plug(150) is contacted with a source/drain region between the gate electrodes through the first interlayer dielectric(140). A conductive material(160) is formed on the semiconductor substrate(100). An anti-diffused reflection layer(180) is formed on the conductive material(160). A photoresist layer is formed on the anti-diffused reflection layer(180). A bit line(160) is formed by etching the anti-diffused reflection layer(180) and the conductive material(160). The second interlayer dielectric(200) is formed thereon. A photoresist layer(220) is formed on the patterned anti-diffused reflection layer(180). An exposure process is performed by using an exposure mask(240) with a storage electrode pattern(250). The storage electrode pattern(250) is printed on the photoresist layer(220). An opening for storage electrode is formed by etching the second and the first interlayer dielectrics(220,140).