| 摘要 |
PROBLEM TO BE SOLVED: To reduce jitters of a sampling clock and a data symbol clock, which are accompanied by band narrowing, in sampling processing. SOLUTION: The system band of an IF signal is sampled in a batch by an A/D converter 110 and converted into a digital signal, and a signal in a specific channel frequency band is extracted through a filter part 210, and data thinning-out is operated by a re-sampling part 220 so that signal quantity can be reduced. Then, the output signal of the re-sampling part 220 is subjected to phase comparison with a preliminarily held reference signal, and the clock frequencies of a sampling clock generator 120 are controlled, so that frequency errors and phase errors is eliminated, based on the result of the phase comparison by a clock phase error detecting part 230. |
