| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a delay signal giving no influence on voltage dependency and being suitable for power source voltage. SOLUTION: This device is provided with a power source voltage detecting means and a delay means adjusting delay quantity by power source voltage, and the delay means is constituted of a delay section in which inverters 5a of two stages and four stages are connected and transfer gates 8, 9 consisting of P/NMOS transistors of which a control terminal is connected to an output of the power source voltage detecting means. An adjusted delay signal can be outputted by receiving a signal in accordance with power source voltage from the power source voltage detecting means at a control terminal of the transfer gate, selecting two stages or four stages of the delay section, and outputting it.</p> |
