| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a clock phase-locked loop device in which glitches are not generated. SOLUTION: This DLL circuit is provided with a delay clock signal output circuit for outputting reference clock signals delayed for specified time stepwise, corresponding to the deviation of the phases of the reference clock signals inputted to an input terminal and delayed reference clock signals fed back from the end of a clock tree and a data latch circuit operated for a fixed period, when the delay time of the reference clock signals outputted by the delay clock signal output circuit is changed.</p> |
