| 摘要 |
Improved systems and methods of phase detecting are described. In one aspect, a phase detector (12) includes a latch (30, 32) having an input stage (50) and an output stage (52). The input stage (50) couples to the output stage (52) through a dynamic storage node (54) and includes a discharge circuit (58). The discharge circuit (58) has a first input (60) and a second input (64) and defines a discharge path for discharging the dynamic storage node (54) that is substantially symmetric with respect to the first and second input (60, 64). In another aspect, the dynamic storage node (54) is discharged with a characteristic discharge time in response to a transition of the first input (60) from a low logic level to a high logic level when the second input (64) is at a high logic level. The dynamic storage node (54) also is discharge with substantially the same characteristic discharge time in response to a transition of the second input (64) from a low logic level to a high logic level when the first input (60) is at a high logic level.
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