发明名称 POWER DISSIPATION CONTROL MECHANISM FOR CPU
摘要 <p>A power dissipation control mechanism for a central processing unit includes a power estimation circuit for estimating the power dissipation of instructions executed by the central processing during a selected time interval and a speed controller for adjusting the speed of the central processing unit in response to the estimated power dissipation produced by the power estimation circuit.</p>
申请公布号 WO2002027450(A2) 申请公布日期 2002.04.04
申请号 US2001029984 申请日期 2001.09.26
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