| 摘要 |
An improved sub 8F<2> memory cell is disclosed. The sub 8F<2> cell includes a trench capacitor (260) formed in a substrate; a shallow transistor trench (STT) (287) formed in the substrate; a transistor comprising a first diffusion region (213), the first diffusion region couples the transistor to the gate, a second diffusion region (214), the second diffusion region couples the transistor to a bit line, and a gate (212) serving as a word line, the gate includes a buried portion and a non-buried portion, wherein the buried portion of the gate occupies the shallow transistor trench. |
