发明名称 CASCADE CIRCUIT
摘要 <p>The present invention relates generally to electrical cascade circuits using normally-off junction field effect tansistors (JFETs) which have low on-resistance for low voltage and high current density applications. Proper configuration of the normally-off JFETs allows for low voltage drop, low-on resistance, high current density and high frequency operations. More particularly, these cascade circuits are configured to provide amplification of an input signal and signal switching capabilities. In general two or more normally-off JFETs are coupled together on a substrate to create a desired characteristic. For a three terminal gate-controlled cascade amplification circuit, an input signal at the first JFET can realize a signal gain of 80dB to 120dB at the second JFET. A four terminal gate-controlled cascade switching circuit, comprised of two JFETs, switches on or off to regulate current flow through the second JFET.</p>
申请公布号 WO2002027796(A2) 申请公布日期 2002.04.04
申请号 US2001030497 申请日期 2001.09.28
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址