Semiconductor memory device and bit line isolation gate arrangement method thereof

摘要

State change transition times of a semiconductor memory device is reduced by reducing contact resistance associated with unshared input/output (I/O) lines. To minimize the difference in transition times between shared I/O lines having dual precharging circuits and non-shared I/O lines which have only a single precharging circuit, effective contact resistance of the non-shared I/O lines are reduced by eliminating unnecessary isolation gates with their attendant impedances. This provides faster transition times for the non-shared I/O lines.