| 摘要 |
<p>The present invention relates to a pipelined microprocessor for processing instructions, comprising at least one pipeline comprising an instruction fetching functional stage (1), an instruction decoding functional stage (2), an execution functional stage comprising a number of execution units (4A, 4B, 4C) and a commit functional stage (5) comprising or being associated with a reorder buffer (10). Detecting means (8C) are provided for detecting instruction irregularities. When an instruction irregularity is detected, an irregularity indication and a flush instruction are generated. The irregularity indication is used to initiate a flush mode whereas the flush instruction, when received in a stage or unit set in flush mode, resets the flush mode in said stage/unit.</p> |
