发明名称 Image processing circuit
摘要 CCD data is compressed by compression means and stored in a raw image data buffer (step 10). Then, the compressed data is expanded by expansion means, so that pixel data thereof is sequentially output to an RPU (step 11). The RPU executes real-time image processing on the pixel data, so that the processed data is stored in a processed data buffer in units of frames. Then, a CPU reads an image from the processed data buffer at a proper timing and performs software processing such as high-efficiency coding through a temporary storage data buffer, for storing and preserving the processed data in a storage medium (step 12). Thus provided is an image processing circuit capable of reducing the scale of buffer areas in a memory for remarkably reducing the cost for the memory as well as power consumption.
申请公布号 US2002039143(A1) 申请公布日期 2002.04.04
申请号 US20010964458 申请日期 2001.09.28
申请人 MEGA CHIPS CORPORATION 发明人 SASAKI GEN
分类号 H04N5/14;H04N1/21;H04N1/41;H04N5/232;H04N5/335;H04N5/361;H04N5/367;H04N5/378;H04N7/26;H04N9/64;H04N101/00;(IPC1-7):H04N7/12 主分类号 H04N5/14
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