METHOD AND LOW-POWER CIRCUITS USED TO GENERATE ACCURATE DRAIN VOLTAGE FOR FLASH MEMORY CORE CELLS IN READ MODE

摘要

Control circuitry and a method for generating an accurate drain voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Select gate transistors (SG1 SGm) are provided which have their conduction path being coupled between a power supply voltage and a drain of one of the selected memory core cells. A differential amplifier circuit (202) is responsive to a bitline voltage corresponding to a drain voltage of the selected memory core cells and a reference voltage for generating a select gate voltage. The select gate voltage is decreased when the bitline voltage is higher than a target voltage and is increased when the bitline voltage is lower than the target voltage. A source follower circuit (204) is responsive to the select gate voltage for generating the bitline voltage which is maintained at the target voltage. The control gates of the select gate transistors are connected to receive the select gate voltage for maintaining the voltage at the drain of the selected memory core cells to be approximately constant.