| 摘要 |
In a data processing apparatus, an image memory has a descriptor region and an image region, the image region storing a plurality of blocks of image data, the descriptor region storing a corresponding number of descriptor information blocks for the plurality of image data blocks. A DMA controller controls DMA data transfer of the image data blocks from the image region according to each descriptor information block in the descriptor region. The DMA controller comprises a register which stores one of the descriptor information blocks from the descriptor region of the image memory, and a control unit which determines, at a time of occurrence of a CPU interrupt, a start timing of a DMA data output operation of the DMA controller during a DMA data input operation of the DMA controller when an image editing request contained in input image data is received, the CPU interrupt being caused to occur by an interrupt request bit of the descriptor information block read from the register. <IMAGE> |
