Delay locked loop for use in semiconductor memory device

摘要

A delay locked loop (DLL) is disclosed which has finer adjustability. The delay locked loop generally includes: a first shift register (330) for controlling a delay amount of an internal clock in response to a first shift-right signal and a first shift-left signal, a first delay line (340) for delaying the internal clock according to an output of the first shift register, wherein the first delay line includes a plurality of first delay units, each first delay unit having a first delay amount; a second shift register (350) for controlling the delay amount of an output of the first delay line in response to a second shift-right signal and a second shift-left signal, which are outputted from the first shift register; and a second delay line (360) for delaying an output of the first delay line by a predetermined delay amount in response to an output of the second shift register, wherein the second delay line includes a plurality of second delay units, each second delay unit having a second delay amount larger than the first delay amount.