Silicon rich oxides and fluorinated silicon oxide insulating layers

摘要

Silicon rich oxide barrier layers are used to encapsulate metal interconnects in an integrated circuit. The barrier layers prevent fluorine diffusing out of a low-k fluorinated silicon glass (FSG) interlayer dielectric which would otherwise react with and damage the metal interconnects. The dielectric layers are deposited using a high density plasma CVD method which can cause the formation of raised bumps 320 over buried features 110. Features greater than about 5000nm in width are difficult to flatten using chemical mechanical polishing, so a photolithographic etching step is used to remove most of such raised features. Subsequently, the ILD may be planarized by CMP.