发明名称 |
Semiconductor integrated circuit and manufacturing method therefor, semiconductor macro cell and automatic layout method therefor, and mask processing method |
摘要 |
In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.
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申请公布号 |
US6367061(B1) |
申请公布日期 |
2002.04.02 |
申请号 |
US19990413481 |
申请日期 |
1999.10.06 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KUROKAWA KEIICHI;TAKAHASHI MIWAKA;FUKUMOTO MINAKO;KOSHITA NORIKO;TOYONAGA MASAHIKO |
分类号 |
G06F17/50;G06F19/00;G06G7/66;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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