| 摘要 |
The invention relates to reference handover in clock signal generation systems and similar applications. The idea according to the invention is to introduce a so-called "virtual" delay in the control loop of a PLL for the purpose of forcing the control loop to shift the phase of the PLL output clock signal, while still maintaining the mandatory phase lock condition of the PLL relative to a primary reference signal, towards a predetermined target phase relation with the primary reference signal. By utilizing a virtual delay, the problems associated with explicit delay elements such as passive or active delay lines are avoided, and a more robust and accurate clock phasing mechanism is obtained. Preferably, the virtual is introduced by superimposing an external phasing control signal in the control loop of the PLL on the output signal/input signal of a control loop element.
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