发明名称 |
Self aligned dual damascene method |
摘要 |
A method for fabricating an interconnection between a conductive line and a via plug on an insulating layer, comprises the steps of: forming a conductive line pattern on the insulating layer; etching the upper part of the insulating layer and forming a conductive line opening; forming conductive line spacers to provide better alignment between the conductive line and the via, to provide better control of a small via, and to help the metal to have better coverage effects in filling in the conductive line opening and the via; producing a via pattern on the insulating layer and the via pattern opening being substantially larger than the conductive line opening; etching the exposed lower part of the insulating layer by utilizing the conductive line spacers as an etching mask and forming a via hole; and filling the conductive line opening and the via hole with a conductive material and forming an interconnection of the conductive line and a via plug.
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申请公布号 |
US6365504(B1) |
申请公布日期 |
2002.04.02 |
申请号 |
US19990418840 |
申请日期 |
1999.10.15 |
申请人 |
TSMC-ACER SEMICONDUCTOR MANUFACTURING CORPORATION |
发明人 |
CHIEN WU KUO;CHIEH CHEN HSI;PING CHEN HAN |
分类号 |
H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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