| 摘要 |
A ceramic capacitor typically 10 mils to 340 mils square by typically 4-20 mils thickness with areas of metallization, or pads, to which electrical connections may be made on, typically, each of two opposite exterior surfaces, has embedded at least one, and normally two or more, metallization planes at close, typically 0.5 mil, separation. Each interior metallization plane connects through multiple redundant vias, as are preferably made by (i) punching, (ii) drilling, (iii) laser drilling, or (iv) radiation patterning of a green ceramic sheet having a photosensitive binder, to an associated surface pad or trace. The vias are both numerous and redundant, typically being of 2 mil diameter on 10 mil centers in a pin grid array pattern over and through entire ceramic layers of the capacitor, permitting both (i) easy fabrication without exacting alignment or registration between layers, and (ii) low Equivalent Series Resistance (ESR) in the finished capacitor. The composite structure so created exhibits increased capacitance over that which would alternatively exist should no electrically-connected interior metallization planes be present.
No longer being required to be maximally large for optimum capacitance, the exterior pads are well-sized and well-located, and are preferably withdrawn form the edges of the capacitor both so as to prevent wicking of epoxy adhesive and so as to permit rounding the edges of the capacitor in order to inhibit chipping. The reduced-size pads are nonetheless much larger than are the multiple vias redundantly electrically connecting to each, and are readily reliably electrically connected, normally by smoldering.
|
