发明名称 |
Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids |
摘要 |
A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask. A passivation layer is deposited overlying the conductive layer and the dielectric layer. The integrated circuit device is completed.
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申请公布号 |
US6365464(B1) |
申请公布日期 |
2002.04.02 |
申请号 |
US19990318470 |
申请日期 |
1999.05.25 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
CHIANG MING-HSIUNG;WU JAMES;LEE YU-HUA |
分类号 |
H01L21/768;(IPC1-7):H10L21/336 |
主分类号 |
H01L21/768 |
代理机构 |
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地址 |
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