发明名称 Processor bus arrangement
摘要 A processor bus has several data processing units, each connected to a line system which acts as a bus having bus segments connected in a separable manner through connection units. Functional units arranged on the bus carry out the information thereof. The functional units may carry out exchanges independently of each other. Conversely, functional units in different groups may carry out information exchanges simultaneously. The connection units define combinatory connections of the signal lines, with physical connections between the connection units provided by the bus segments. The connection units can carry out information exchanges with as many connected functional units as desired. The information path from a functional unit to selected functional units can be multiplexed or switched by toggling simultaneous connections to several functional units or by bridging non-participating functional units.
申请公布号 AU1036902(A) 申请公布日期 2002.04.02
申请号 AU20020010369 申请日期 2001.09.21
申请人 SYSTEMONIC AG 发明人 WOLFRAM DRESCHER;GERHARD FETTWEIS
分类号 G06F13/36;G06F13/40 主分类号 G06F13/36
代理机构 代理人
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