| 摘要 |
An improved clock generation circuit is provided that operates with a single input clock frequency, and includes a Phase Locked Loop circuit (PLL) with a digital accumulator in the feedback loop, in which either the Most Significant Bit or the Carry Bit of the binary adder is used as the modulated feedback clock to the phase/frequency detector of the PLL. In one embodiment, a fixed add/phase amount is used to drive one of the inputs of the binary adder to generate a fixed output frequency. If it is desired to modulate the output frequency, then an Add Amount Modulator circuit can be provided that presents a varying numeric value to one of the inputs of the binary adder. The MSB or Carry Bit is communicated to an address look-up table, which then outputs an address to a memory circuit, which in turn presents a different add amount to the binary adder. If a periodic modulation is desired, the address look-up table will point to add amounts that create a particular periodic output frequency profile, which could include a Spread Spectrum profile. Certain optional circuits may be included, such as: a pre-multiply or pre-divide circuit to either increase or decrease the frequency of the input clock signal before it reaches the phase/frequency detector of the PLL; an output divider to provide a lower output clock frequency; a feedback divider to lower the VCO's output frequency before it is directed into the digital accumulator; a synchronizing input (Sync Input); a synchronizing output (Sync Output); a Base Number register to keep the memory size of the look-up table to a reasonably small value; or a Start Number register to provide the add amount upon initialization.
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