发明名称 Unlanded vias with a low dielectric constant material as an intraline dielectric
摘要 A method of fabricating an unlanded via over a polymer that is used as an intraline or intralayer dielectric is described. In one embodiment, the present invention creates an etch-stop layer for forming unlanded vias using three steps. A recess is created in an intraline dielectric, such as an organic polymer. An etch-stop layer is then deposited over the intraline dielectric. The etch-stop layer is then polished back before depositing a final insulating layer. The unlanded via is formed by etching through the final insulating layer. The intraline dielectric is protected by the etch-stop layer during the etch of the final insulating layer to form the unlanded via.
申请公布号 US6365971(B1) 申请公布日期 2002.04.02
申请号 US19990318704 申请日期 1999.05.26
申请人 INTEL CORPORATION 发明人 BAI GANG
分类号 H01L21/60;H01L21/768;H01L23/522;(IPC1-7):H01L23/48;H01L23/52 主分类号 H01L21/60
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