Integrated circuit memory having column redundancy with no timing penalty

摘要

A memory array includes a zone of memory elements and a column multiplexer. The zone of memory elements is arranged in rows and columns, including a set of non-redundant columns and a redundant column. The column multiplexer has a section coupled to the set of non-redundant columns and to the redundant column. The column multiplexer has a selectable non-redundant path through the section for each of the non-redundant columns and a selectable redundant path for the redundant column. The redundant path is interchangeable with any one of the non-redundant paths.