| 摘要 |
PROBLEM TO BE SOLVED: To provide a circuit designing method and device for effectively reducing power consumption by selectively gated clocking an F/F. SOLUTION: This method comprises a step (2) for searching the operation condition of an F/F by analyzing RTL description, and for extracting an enable signal, a step (3) for changing the RTL description into RTL description indicating the corresponding relation of the enable signal and the F/F, a step (5) for inputting the changed RTL description and test vectors, and for simulating this circuit, a step for searching an active rate being a rate at which an enable state is obtained from the simulated result, a step (7) for changing the F/F to the gated clocked F/F based on the active rate, and a step (8) for outputting the result as the RTL description.
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