| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem where a power source voltage of a buffer constituting a clock tree is changed by arrangement positions of the buffer and the required time of a clock signal to a clock pin of a flip-flop is largely changed, so that timing error may be generated in the conventional standard cell system LSI. SOLUTION: In a standard cell system LSI, power source wirings are formed by arranging standard cells 201 which have two power source wirings and two ground wirings in a line type. A buffer 208 constituting a buffer tree is connected with a second power source wiring 205 and a second ground wiring 207. The other cells 201 are connected with a first power source wiring 204 and a first ground wiring 206. By using the above constitution, voltage drop in the power source wiring through which a power is supplied to the buffer 208 constituting the clock tree and voltage increase in the ground line can be reduced, so that irregularity of the required time of a clock signal to a clock pin of a flip-flop 209 can be reduced.
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