发明名称 SEMICONDUCTOR MEMORY AND SENSE AMPLIFIER CONTROL METHOD THEREFOR, AND BIT LINE FAILURE DETECTION METHOD
摘要 PROBLEM TO BE SOLVED: To accurately detect a bit line bridging failure, and also improve a failure detection rate. SOLUTION: In a test mode, 1st- and 2nd sense amplifier control signals PSE-01, PSE-E are enabled at different points of time, and the 1st sense amplifier 320 for detecting and amplifying the potentials of an odd-numbered bit line pair and the 2nd sense amplifier 330 for detecting and amplifying an even- numbered bit line pair are activated at different points of time. Namely, in the test mode, the odd-numbered bit line pair BL1, BL1B and the even-numbered bit line pair BL2, BL2B are made to differ in sensing point of time. In the test mode, when the odd-numbered sensing pair have been sufficiently sensed, the sensing of the even-numbered bit line pair BL2, BL2B are performed.
申请公布号 JP2002093200(A) 申请公布日期 2002.03.29
申请号 JP20010201441 申请日期 2001.07.02
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 LEE HYONG-YONG;JUN SUK-BAE;PARK CHOONG-SUN
分类号 G01R31/28;G11C11/401;G11C11/409;G11C29/02;G11C29/12;(IPC1-7):G11C29/00 主分类号 G01R31/28
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