| 摘要 |
PROBLEM TO BE SOLVED: To provide a control circuit of a DRAM in which an access time can be shortened by separating control of delivery and reception of data from access control of a DRAM and starting the next access even in a halfway point of delivery and reception of data. SOLUTION: When read-processing of data is required from a SDRAM 21 by the instruction of a CPU 22 or access is required from a DMA while write- processing of data is performed, the requirement is informed to a bus orbiter 33, a SRAM control section 34 starts processing for access requirement of the DAM even if read-out or write-in of data is being performed by the instruction of the CPU 22. In such a constitution, access for the SDRAM is performed at high speed and processing speed for the DRAM is improved. |
