发明名称 SEMICONDUCTOR MEMORY AND OPERARTING METHOD
摘要 PROBLEM TO BE SOLVED: To reduce a bit cost of a CAM cell by decreasing the number of elements and dispersing with wiring supplying fixed voltage. SOLUTION: This device has a first write-in transistor Mw1 of which a gate is connected to a word line WL and a drain is connected to a first bit line BL, a second bit line /BL of which a gate is connected to the word line WL and a drain is connected to a second bit line /BL, a first retrieving transistor Ms1 connected between the first bit line BL and a match line ML and of which a gate is connected to a storage node SN1, a second retrieving transistor Ms2 connected between the second bit line /BL and a match line ML and of which a gate is connected to a storage node SN2, and first and second capacitors C1, C2 connected between gates of the first and the second retrieving transistors Ms1, Ms2 and the match line ML.
申请公布号 JP2002093178(A) 申请公布日期 2002.03.29
申请号 JP20000278636 申请日期 2000.09.13
申请人 SONY CORP 发明人 EMORI TAKAYUKI
分类号 G11C15/04;H01L21/8242;H01L27/108 主分类号 G11C15/04
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