发明名称 CIRCUIT FOR OPERATING PLURALITY OF CPUS
摘要 PROBLEM TO BE SOLVED: To provide a circuit in which a memory for program storage and a port for loading are connected, a plurality of CPUs are operated and the program of each CPU can be loaded into a RAM in a short time. SOLUTION: In this circuit in which buses 3 and 4 connected respectively to two or more CPUs 1 and 2 are communicable through a data storing means 5, a program for operating the respective CPUs is stored in a flash memory 9, the program is loaded to RAMs 6 and 7 connected to the buses 3 and 4 connected to the CPUs 1 and 2, and the respective CPUs 1 and 2 are operated by the program on the respective RAMs 6 and 7 at the time of operating the respective CPU, the bus 3 and the bus 4 are connected through a 1st switch 10 and another switch 11 is arranged between the CPU 2 and the bus 4.
申请公布号 JP2002091935(A) 申请公布日期 2002.03.29
申请号 JP20000282864 申请日期 2000.09.19
申请人 KENWOOD CORP 发明人 NISHIMURA YOSHIHIRO
分类号 G06F15/177;G06F9/06;G06F13/16;G06F13/36;G06F15/167;(IPC1-7):G06F15/177 主分类号 G06F15/177
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