| 摘要 |
PROBLEM TO BE SOLVED: To perform quantitative analysis by estimating influence of a parasitic element before layout design. SOLUTION: In layout design of an analog circuit, a process S1 for extracting a circuit net list 1, a process S2 for inserting virtual parasitic resistance in the circuit net list, and a process S3 wherein simulation is executed and arrangement wiring restriction is derived, are included.
|
