| 摘要 |
PROBLEM TO BE SOLVED: To provide a burn-in method and apparatus which can accelerate burn-in, not only in a memory cell array part but also even a peripheral circuit part or logic circuit part. SOLUTION: A high-temperature stress is applied to a wafer to be evaluated (step SP11). Low-temperature stress and electrical stress are then applied to the wafer (step SP12). Next, it is determined whether prescribed stress has been applied to the wafer (step SP13). If the determination result of the step SP13 is 'YES', then it is determined whether a fault has occurred in the chips of the wafer (step SP14). With respect to the chip which is determined as having a fault therein based on the determination result of the step SP14, it is determined whether the fault location is to be relieved (step SP15). If the determination result of the step SP15 is 'YES', then the relief of the fault location is carried out (step SP16).
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