发明名称 DATA TRANSMITTING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a method for compensating delay time fluctuations, depending on a data pattern due to the connection of wiring traveling in parallel, and for making multiple data transmission signals reach a receiver circuit with a fixed delay time at the same time, in signal transmission between circuit blocks in an integrated circuit. SOLUTION: In multiple parallel wiring, mutually having connection for connecting the circuit blocks of a semiconductor integrated circuit, the signal transmission timing of a driver circuit is decided according to the level of connection of the parallel wiring and the transition directions of signals to be transmitted on the parallel wiring, so that the signals are made to arrive at a receiver circuit at the same time by a delay quantity decision circuit 151, and the timing of a clock signal to be applied to a driver circuit is controlled with a timing corresponding to the output of the delay quantity decision circuit by a timing control circuit 152. Then, the timing of data to be outputted with by the driver circuit can be changed dynamically.</p>
申请公布号 JP2002094489(A) 申请公布日期 2002.03.29
申请号 JP20000286843 申请日期 2000.09.18
申请人 HITACHI LTD 发明人 SATO TAKASHI
分类号 G06F13/42;H01L21/822;H01L27/04;H04L7/00;H04L25/40;(IPC1-7):H04L7/00 主分类号 G06F13/42
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