发明名称 SIGNAL DELAY ANALYZING METHOD UNDER CONSIDERATION OF CROSS TALK AND DELAY IMPROVING METHOD USING THE SAME AND LSI DESIGNING METHOD
摘要 PROBLEM TO BE SOLVED: To detect and improve a place having a large effect of cross talk on delay under the consideration of signal transition and a timing. SOLUTION: A resistance and capacity network is defined under the consideration of a coupling capacity on which signal transition is reflected, and timing analysis is linked so that delay calculation can be operated. Then, the coupling capacity is redefined based on a newly calculated timing analytic result so that the resistance and capacity network can be generated, and the delay calculation and timing analysis are operated again. This operation is repeated, and delay fluctuation amounts are detected so that the place where the effect of cross talk is likely to be generated can be specified. Also, the effect of the cross talk can be analyzed in the early stage of LSI design by using the resistance capacity network in deciding rough wiring paths after cell arrangement.
申请公布号 JP2002092069(A) 申请公布日期 2002.03.29
申请号 JP20000281196 申请日期 2000.09.18
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAWAKAMI YOSHIYUKI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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