| 摘要 |
PROBLEM TO BE SOLVED: To provide a phase comparator circuit with a maximum operating frequency and to provide a phase-locked loop circuit. SOLUTION: This phase comparator circuit 10 is provided with 3 S-R flip-flop circuits 1-3, each consisting of two NAND gates, NAND gates G1-G6 and inverters IV1-IV6. Even if the phase difference between a reference clock signal REFCLK and a clock signal CLK is large, since an UP signal and a DOWN signal in response to the phase difference of both the signals can be outputted, the maximum operating frequency can be set higher than that of the conventional phase comparator circuits. |
