| 摘要 |
<p>A segmented spectrum clock generator (100) provides a signal (300) with a frequency response having multiple segments with a sharp rolloff of at least 10 dB on both sides of each individual segment's peak amplitude across the entire spectrum. A frequency synthesizer (preferably a phase locked loop) generates the output signal (154) by modulating the output frequency at a predetermined rate between a 'lower bound' and an 'upper bound' modulation frequency. To create and control a segmented spectrum profile, a different value is introduced to the feedback counter (138) to force the VCO (134) to emit a new frequency or phase. Programmable pre-divider (114, 136) and post-divider (142) circuits are used on both sides of the feedback counter (138). A microprocessor or logic state machine load values into registers (114, 140, 144) that program the dividers.</p> |
