| 摘要 |
A multi-layer distributed capacitor structure comprises a bottom electrode layer overlying a monolithic substrate, intermediate pairs of layers of film electrode and dielectric material overlying the bottom electrode, and a top pair of layers of a film electrode and dielectric material overlying the intermediate pairs. The structure contains multiple openings, each opening extending from the top pair of layers through the intermediate layers and optionally through said bottom electrode. Each electrode layer also extends laterally beyond and around the entire periphery of the layers positioned above such that the electrode layers bordering on each opening has edges running along the perimeter of the opening which are left exposed for electrical connection to a circuit using wire interconnects. Accordingly, electrode layers can be selectively accessed through openings to provide local decoupling capacitance to the power supply and ground nodes of an integrated circuit flip-chip mounted on the top surface of the structure. Since local electrical connections can be made between the electrode layers within each opening and the integrated circuit logic gates, lead inductance and equivalent series resistance is significantly reduced, effecting improved switching noise reduction. Further, the structure can be configured as a power distribution circuit for an integrated circuit by directly connecting the electrode layers of structure to a circuit power supply and ground through integrated circuit package leads. Since the electrode layers of structure represent substantially planar power and ground planes, this arrangement results in additional reductions in inductance and resistance of the electrical path. |
