发明名称 METHOD FOR MANUFACTURING BUILD-UP MULTI LAYER PRINTED CIRCUIT BOARD USING PHYSICAL VAPOR DEPOSITION.
摘要 PURPOSE: A method for manufacturing a build-up multi layer printed circuit board is provided to obtain fine circuit pattern and highly reliable via-hole by using physical vapor deposition. CONSTITUTION: Manufacturing of a build-up multi layer printed circuit board is initiated by forming a two sides or multi layer center substrate at steps b1 and b2. At step b3, photo developed insulating resin layer(320) is formed on the top side and/or the bottom side of the center substrate. At step b4, a via-hole(330) is formed by exposure/development on the resin layer(320). At step b5, physical/chemical surface treatment is performed. At step b6, physical vapor deposition is performed. At step b7, a metal deposition film(340) is formed on the inside of the via-hole(330) and the surface of the resin layer(320). At step b8, a metal conductor layer(350) is formed by electrical plating on the metal deposition film(340). At step b9, a circuit pattern is formed by etching the metal conductor layer(350). At step b10, the prescribed steps are repeated. At step b11, post processing such as solder resist appliance, marking and boundary physical processing.
申请公布号 KR20020022477(A) 申请公布日期 2002.03.27
申请号 KR20000055264 申请日期 2000.09.20
申请人 VIATEK CO., LTD. 发明人 JUNG, HAE DO;JUNG, HAE WON
分类号 H05K3/46;(IPC1-7):H05K3/46 主分类号 H05K3/46
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