| 摘要 |
<p>In order to provide high stability of the sampling phase in the course of data recovery and clock recovery from a predetermined input signal (Data_IN), a circuit arrangement (1) having a discretization apparatus (2) for data recovery and a discretization apparatus (3) for clock recovery is proposed, in which the two discretization apparatuses each at least have, on the input side, a decision device (40a, 40b; ... 56a, 56b) having an input at which a clock signal (CLOCK_IN) is present and an input at which the predetermined input signal is present, the decision devices both of the discretization apparatus for data recovery and of the discretization apparatus for clock recovery being essentially structurally identical and each comprising at least one comparator (40a, ..., 56a) with a storage device (40b, ..., 56b) assigned thereto. The symmetrical construction of all the decision devices of the circuit arrangement, the said decision devices being arranged on the input side, enables the devices to operate in phase. In addition, it may be provided that the decision devices of both discretization apparatuses are arranged electrically in parallel both with regard to the predetermined input signal and with regard to the clock signal present at the decision devices. <IMAGE></p> |
