SEMICONDUCTOR MEMORY DEVICE HAVING FIXED CAS LATENCY IN NORMAL OPERATION AND VARIOUS CAS LATENCIES IN A TEST OPERATION

摘要

PURPOSE: A semiconductor memory device is provided to operate with a fixed CAS latency in a normal operation and with various CAS latencies in a test mode. CONSTITUTION: A master signal generating part responds to a power-up signal and a latency test signal and generates a pair of master signals. A plurality of fuse information portions operate responsive to the power-up signal and the latency test signal and generate fuse information signals based on whether fused are cut. An MRS address portion includes a plurality of MRS address information portions which operate responsive to address bits of a mode register set and generate MRS address latch signals. A CAS latency determining portion includes a plurality of CAS latency information blocks which operate responsive to a master signal, the fuse information signals, and the MRS address latch signals and generate CAS latency select signals.