Synchronous semiconductor memory device capable for more reliable communication of control signal and data

摘要

In an SDRAM, an unlocked-state detection circuit detects whether synchronization between an external clock signal and an internal clock signal generated in the SDRAM according to the external clock signal is locked. When the internal clock signal is inappropriately locked, a signal output from the SDRAM to a memory controller transitions low, and the controller ignores data received and the SDRAM performs a process to ignore an input command.