发明名称 Apparatus for selectively encoding bus grant lines to reduce I/O pin requirements
摘要 One embodiment of the present invention provides an apparatus that selectively encodes bus grant lines to reduce I/O pin requirements. This apparatus includes a semiconductor chip with bus arbitration circuit. A number of grant lines emanate from the bus arbitration circuit. An encoder circuit encodes the grant lines into a smaller number of encoded grant lines. A selector circuit selects outputs from between the encoded grant lines and a first subset of grant lines. These outputs pass through output pins off of the semiconductor chip. During a first mode of operation, the first subset of grant lines is driven through the plurality of output pins. During a second mode of operation, the encoded grant lines are driven through the output pins. A variation on the above embodiment includes a number of bus request lines, which are divided into a first subset and a second subset. The first subset of request lines feeds through a number of input pins into the bus arbitration circuit. During the first mode of operation, the second subset of request lines feeds from off of the semiconductor chip through a number of I/O pins and bi-directional buffers into the bus arbitration circuit. During the second mode of operation, the second subset of grant lines feeds from the bus arbitration circuit, through the bi-directional buffers and I/O pins and off of the semiconductor chip.
申请公布号 US6363447(B1) 申请公布日期 2002.03.26
申请号 US19990332279 申请日期 1999.06.12
申请人 MICRON TECHNOLOGY, INC. 发明人 LARSON DOUGLAS A.
分类号 G06F13/364;(IPC1-7):G06F13/36 主分类号 G06F13/364
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